The prior art provides a number of ways to stack multi-chip modules (“MCM's”). Two existing packaging technologies in particular address problems typically associated with the stacking of such modules.
The Ultra Thin Stacked Chip Scale Package (UT-SCSP) technology envisions using thinner dice, for example, dice having a height (“z height”) of up to about 3 mils (instead of the usual 4 or 5 mils for a conventional Stack Chip Scale Package), and then stacking about two to about five of such dice. An example of a UT-SCSP is shown in FIG. 1. As seen in FIG. 1, a UT-SCSP module 100 includes a substrate 110 including conductive traces 120 connected to solder balls 130, wirebonds 140 connecting conductive traces 120 to respective ones of the dice 150, the dice being mounted to each other with conventional die attach 160. Dice 150 are embedded in a mold compound 170. UT-SCSP technology allows an increase in package capability and functionality while maintaining specific z-height requirements and the same footprint. For example, UT-SCSP technology offers the possibility of stacking two to five memory die with an optional logic die in a single module. The total module thickness varies from between about 1.0 to about 1.4 mm. However, UT-SCSP technology does not allow a stacking of square-shaped dice without the use of a spacer in between the dice, since the wirebonds of a bottom die would otherwise touch the top die. In addition, and as suggested in FIG. 1, UT-SCSP technology does not allow an optimum package test yield when a defective die is part of the package, to the extent that UT-SCSP technology provides an already stacked module before testing can be effected.
An alternative technology, termed the Folded Stacked Chip Scale Package technology (FS-CSP technology), envisions folding a top package over a bottom package using a folded flop, that is, a flexible substrate with copper traces that is folded for the purpose of interconnection. The top package typically has a land pad which serves as the connection between the top package and the bottom package. An example of an FS-CSP module is shown in FIG. 2. As seen in FIG. 2, a FS-CSP module 200 includes a top package 210 and a bottom package 220. Each of the packages includes a substrate 230 having conductive traces (not shown) connected to solder balls 240, wirebonds 250 connecting conductive traces in the substrate to respective ones of the dice 260, the dice being mounted to each other with conventional die attach (not shown). Dice 260 are embedded in a mold compound 280. FS-CSP technology allows higher test yields with when compared with UT-SCSP technology, to the extent that the bottom and top packages, such as bottom package 220 and top package 210, are assembled separately, thus allowing the packages to be tested prior to stacking. However, FS-CSP technology results in the creation of a module exhibiting bending stresses that tend to crack associated conductive traces, such as conductive traces (not shown) in flexible substrate 290 of module 200, disadvantageously creating the risk of open traces. Another disadvantage of an FS-CSP module is the existence of extended copper traces from the top package to the bottom package, which traces, by virtue of their extended length, tend to cause increase resistances and hence large voltage losses.
One way to package electronic devices together is through the use of a ball grid array (BGA). Among the conventional types of electronic packages, ball grid array (BGA) is most common. A back of a die is attached to the bonding pad on a substrate using an adhesive tape or other nonconductive adhesive materials. The bonding pads on the die and the contact points on the substrate are electrically connected using conductive wires. An encapsulation encloses the die, the conductive wires, and the contacts. In addition, a plurality of solder balls is planted onto the ball pads on the substrate so that the ball grid array may transmit electrical signals to the external circuit through the solder balls. Since the circuit layout on the BGA package is arranged in the form of an array, the package can accommodate a large number of external contacts. FIG. 3 is a schematic cross-sectional view of a conventional cavity down ball grid array package. As shown in FIG. 3, the cavity down ball grid array package 300 includes a substrate 310, a die 320, a plurality of conductive traces 330, wirebonds 335, an encapsulation mold 340 and a plurality of solder balls 350. The solder balls 350 are attached to contacts on the substrate 310. Through the solder balls 350, the substrate 310 can connect electrically with an external circuit (not shown). In a cavity down BGA, as in BGA 300, the die and solder balls are attached on one surface of the substrate, the other surface being available for attachment to a conductive pad, such as a copper pad, or directly to a heat sink for improved thermal and electrical performance. The provision of the die and solder balls on a single surface of the substrate brings about a lower height of the package.
None of the available packaging techniques that allow maintaining height requirements of a package without losing package functionality and capacity.